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PRELIMINARY
PDM31564 PDM31564
256K x 16 CMOS 3.3V Static RAM
Features
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Description
The PDM31564 is a high-performance CMOS static RAM organized as 262,144 x 16 bits. The PDM31564 features low power dissipation using chip enable (CE) and has an output enable input (OE) for fast memory access. Byte access is supported by upper and lower byte controls. The PDM31564 operates from a single 3.3V power supply and all inputs and outputs are fully TTLcompatible. The PDM31564 is available in a 44-pin 400-mil plastic SOJ and a plastic TSOP package for high-density surface assembly and is suitable for use in highspeed applications requiring high-speed storage.
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High-speed access times - Com'l: 8, 10, 12, 15, and 20 ns - Ind: 12, 15, and 20 ns Low power operation (typical) - PDM31564SA Active: 300 mW Standby: 25mW High-density 256K x 16 architecture 3.3V (0.3V) power supply Fully static operation TTL-compatible inputs and outputs Output buffer controls: OE Data byte controls: LB, UB Packages: Plastic SOJ (400 mil) - SO Plastic TSOP (II) - T
Functional Block Diagram
Row Address Buffer Row Decoder Vcc Vss
7
Memory Cell Array 256 xx128 x 32 512 256 x
A8 - A0 A7-A0
8 9 10 11
I/O15-I/O0
Data Input/ Output Buffer
Sense Amp
Column Decoder WE OE UB LB CE
Control Logic Clock Generator
Column Address Buffer
12
A17 - A9 A15-A8
Rev. 1.2 - 3/31/98
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PRELIMINARY
PDM31564
Pin Configuration TSOP (II)
A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 Vcc Vss I/O4 I/O5 I/O6 I/O7 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 Vss Vcc I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 A12 A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 Vcc Vss I/O4 I/O5 I/O6 I/O7 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
SOJ
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 Vss Vcc I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 A12
Pin Description
Name A17-A0 I/O15-I/O0 CE WE OE LB, UB NC Vss VCC Description Address Inputs Data Inputs Chip Enable Input Write Enable Input Output Enable Input Data Byte Control Inputs No Connect Ground Power (+3.3V)
Capacitance (TA = +25C, f = 1.0 MHz)
Symbol CIN CI/O Parameter Input Capacitance Output Capacitance Conditions VIN = VSS VI/O = VSS Max. 6 8 Unit pF pF
NOTE: This parameter is determined by device characterization, but is not production tested.
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Rev. 1.2 - 3/31/98
PRELIMINARY
PDM31564
Operating Mode
Mode Read CE L OE L WE H LB L H L Write L X L L H L Output Disable L L Standby H H X X H X X X H X UB L L H L L H x H X I/O7-I/O0 Output High Impedance Output Input High Impedance Input High Impedance High Impedance High Impedance I/O15-I/O8 Output Output High Impedance Input Input High Impedance High Impedance High Impedance High Impedance Power ICC ICC ICC ICC ICC ICC ICC ICC ISB
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NOTE: H = VIH, L = VIL, X = DON'T CARE
Absolute Maximum Ratings (1)
Symbol VTERM TBIAS TSTG PT IOUT Tj Rating Terminal Voltage with Respect to VSS Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Maximum Junction Temperature
(2)
Com'l. -0.5 to +4.6 -55 to +125 -55 to +125 1.5 50 125
Ind. -0.5 to +4.6 -65 to +135 -65 to +150 1.5 50 145
Unit V C C W mA C
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Appropriate thermal calculations should be performed in all cases and specifically for those where the chosen package has a large thermal resistance (e.g., TSOP). The calculation should be of the form: Tj = Ta + P * ja where Ta is the ambient temperature, P is average operating power and ja the thermal resistance of the package. For this product, use the following ja values: SOJ: 59o C/W TSOP: 87o C/W
Recommended DC Operating Conditions
Symbol VCC VSS Industrial Commercial Description Supply Voltage Supply Voltage Ambient Temperature Ambient Temperature Min. 3.0 0 -40 0 Typ. 3.3 0 25 25 Max. 3.6 0 85 70 Unit V V C C
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Rev. 1.2 - 3/31/98
PRELIMINARY
PDM31564
DC Electrical Characteristics (VCC = 3.3V 0.3V)
Symbol ILI ILO VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 8 mA, VCC = Min. IOH = -4 mA, VCC = Min. Test Conditions VCC = Max., VIN = Vss to VCC VCC= Max., CE = VIH, VOUT = Vss to VCC Com'l/ Ind. Com'l/ Ind. Min. -5 -5 -0.3(1) 2.2 -- 2.4 Max. 5 5 0.8 Vcc + 0.3 0.4 -- Unit A A V V V V
NOTE: 1. VIL(min) = -3.0V for pulse width less than 20 ns.
Power Supply Characteristics
-8 Symbol Parameter ICC Operating Current CE = VIL f = fMAX = 1/tRC VCC = Max. IOUT = 0 mA ISB Standby Current CE = VIH f = fMAX = 1/tRC VCC = Max. ISB1 Full Standby Current CE VCC - 0.2V f=0 VCC = Max., VIN VCC - 0.2V or 0.2V 10 10 10 15 10 15 10 15 mA 50 45 40 45 35 40 30 35 mA -10 -12 Ind. 210 -15 Com'l 190 Ind. 200 -20 Com'l Ind. 185 195 Unit mA Com'l Com'l Com'l 220 210 200
NOTES: All values are maximum guaranteed values.
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Rev. 1.2 - 3/31/98
PRELIMINARY
PDM31564
AC Test Conditions
Input pulse levels Input rise and fall times Input timing reference levels Output reference levels Output load VSS to 3.0V 2.5 NS 1.5V 1.5V See Figures 1 and 2
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+3.3V 317 DOUT 351 30 pF
+3.3V 317 DOUT 351 5 pF
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Figure 1. Output Load
Figure 2. Output Load Equivalent (for tLZCE, tHZCE, tLZWE, tHZWE, tLZBE, tHZBE, tLZOE, tHZOE)
Rev. 1.2 - 3/31/98
5
PRELIMINARY
PDM31564
Read Timing Diagram
tRC ADDRESSES tAA tACE CE tAOE OE tBA UB, LB tLZBE(1) tLZOE(1) tLZCE(1) DOUT Output Data Valid tHZBE(1) tHZOE(1) tHZCE(1) tOH
AC Electrical Characteristics
Description READ Cycle Symbol Min -8* Max Min -10* Max Min -12 Max Min -15 Max Min -20 Max Unit
READ cycle time Address access time Chip enable access time Byte access time Output hold from address change Byte disable to output in low-Z(1) Byte enable to output in high-Z(1) Chip enable to output in Chip disable to output low-Z(1)
tRC tAA tACE tBA tOH tLZBE tHZBE tLZCE tHZCE tAOE tLZOE tHZOE
8 - - - 4 0 - 3 - - 0 -
- 8 8 5 - - 4 - 4 4 - 4
10 - - - 4 0 - 3 - - 0 -
- 10 10 6 - - 5 - 5 5 - 5
12 -- -- -- 4 0 -- 4 -- -- 0 --
-- 12 12 7 -- -- 8 -- 6 6 -- 5
15 -- -- -- 4 0 -- 4 -- -- 0 --
-- 15 15 8 -- -- 9 -- 7 7 -- 6
20 -- -- -- 4 0 -- 5 -- -- 0 --
-- 20 20 9 -- -- 9 -- 8 10 -- 6
ns ns ns ns ns ns ns ns ns ns ns ns
high-Z(1, 2)
Output enable access time Output enable to output in Output disable to output in * VCC = 3.3V +5% low-Z(1) high-Z(1, 2)
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Rev. 1.2 - 3/31/98
PRELIMINARY
PDM31564
Write Cycle 1 Timing Diagram (WE Controlled)
tWC ADDRESSES tAW tAS WE tCW CE tBW UB, LB tHZWE(1) DOUT (3) High Impedance tLZWE(1) (4) tDH tWP tAH
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tDS DIN Data Stable
Write Cycle 2 Timing Diagram (CE Controlled)
tWC ADDRESSES tAW tAS WE tCW CE tBW UB, LB tLZBE(1) tLZCE(1) DOUT tDS DIN Data Stable tHZWE(1) High Impedance tWP tAH
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tDH
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Rev. 1.2 - 3/31/98
7
PRELIMINARY
PDM31564
Write Cycle 3 Timing Diagram (UB, LB Controlled)
tWC ADDRESSES tAW tAS WE tCW CE tBW UB, LB tLZCE(1) tLZBE(1) DOUT tDS DIN Data Stable tHZWE(1) High Impedance tDH tWP tAH
AC Electrical Characteristics
Description WRITE Cycle WRITE cycle time Chip enable to end of write Address valid to end of write Byte pulse width Address setup time Address hold from end of write Write pulse width Data setup time Data hold time Byte disable to output in low Z(1, 3, 4) Byte enable to output in high Z(1, 3, 4) Output disable to output in low Z(1, 3, 4) Output enable to output in high Z(1, 3, 4) Write disable to output in low Z(1,3, 4) Write enable to output in high Z(1, 3, 4) * VCC = 3.3v +5% Sym tWC tCW tAW tBW tAS tAH tWP tDS tDH tLZBE tHZBE tLZOE tHZOE tLZWE tHZWE -8* -10* -12 -15 -20
Min. Max Min. Max Min. Max. Min. Max. Min. Max. Unit 8 7 7 7 0 0 7 5 0 0 -- 0 -- 0 -- -- -- -- -- -- -- -- -- -- -- 6 -- 6 -- 6 10 8 8 8 0 0 8 6 0 0 -- 0 -- 0 6 -- -- -- -- -- -- -- -- -- -- 6 -- 6 -- -- 12 10 10 10 0 0 8 7 0 0 -- 0 -- 0 -- -- -- -- -- -- -- -- -- -- -- 7 -- 7 -- 7 15 11 11 12 0 0 9 8 0 0 -- 0 -- 0 -- -- -- -- -- -- -- -- -- -- -- 8 -- 7 -- 7 20 13 13 13 0 0 10 9 0 0 -- 0 -- 0 -- -- -- -- -- -- -- -- -- -- -- 9 -- 8 -- 9 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Rev. 1.2 - 3/31/98
PRELIMINARY
PDM31564
NOTES: 1. Parameter is determined by device characterization and is not production tested. See Figure 2 for load conditions. 2. If the CE LOW transition occurs coincident with or after the WE LOW transition, outputs remain in a high impedance state. 3. If the CE HIGH transition occurs coincident with or after the WE HIGH transition, outputs remain in a high impedance state. 4. If OE is HIGH during a write cycle, the outputs are in a high-impedance state during this period.
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Ordering Information
XXXXX X
Device Type
Power
XX X Speed Package Type
X
X
Process Temp. Range
Preferred Shipping Container Blank Tubes TR Tape & Reel TY Tray Blank Commercial (0 to +70C) I Industrial (-40C to +85C) A Automotive ( -40C to +105C) SO T 8 10 12 15 20 44-pin 400-mil Plastic SOJ 44-pin Plastic TSOP (II) Commercial Only Commercial Only
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SA
Standard Power
PDM31564 - (256Kx16) Static RAM
Faster Memories for a FasterWorld TM
Rev. 1.2 - 3/31/98 9

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